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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
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MC143421
Advance Information
PCI Bus Interface
The MC143421 PCI Bus Interface chip is a low cost and highly integrated PCI interface solution that includes Advanced Configuration Power Interface (ACPI) features. It is designed to enable the addition of a PCI interface to PC peripherals such as DSP-based analog modems. The Peripheral Interface Bus (PIB) that interfaces this device to the PC peripheral function provides four address lines, byte-wide data, and eight programmable lines that can be used for chip selects, interrupts, and power-down enable. Features * Fully Compliant 32-Bit PCI 2.1 Interface * Four Address Lines and Byte-Wide Data * Eight General Purpose I/O Lines * ACPI Power Management and OnNowTM Support * Single Digital 100-Pin QFP VLSI Implementation BLOCK DIAGRAM
FU SUFFIX QFP CASE 842D
ORDERING INFORMATION
MC143421FU QFP
PME# INTERRUPT AUX PIN CONTROL REGISTER AUX[7:0]
PCI BUS
PCI CONFIGURATION REGISTER DATA REGISTER/DEMUX DATA
AD[31:0]
ADDRESS DECODE/DEMUX
ha[3:0]
This document contains information on a new product. Specifications and information herein are subject to change without notice.
All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.
REV 0 2/98 TN98022400
(c) Motorola, Inc. 1998 MOTOROLA
PERIPHERAL INTERFACE BUS (PIB)
CNTL
SYSTEM CONTROL LOGIC
PIB CONTROL
MC143421 1
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Symbol Tstg TA V Parameter Value Unit C C V Storage Temperature Range - 65 to 150 - 25 to 75 Operating Temperature Range Voltage Range on Any Pin - 0.5 to 5.5
MAXIMUM RATINGS (Voltages Referenced to VSS)
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit.
RECOMMENDED OPERATING CONDITIONS
Symbol TA VCC
Parameter
Min 0 4.75
Max 70 5.25
Unit C V
Operating Temperature Range Supply Voltage
DC CHARACTERISTICS (Over the Recommended Operating Conditions)
Symbol VIH VIL VCH VCL VOH VOL ILI IIO Cin Cout CCLK Characteristic High Level Input Voltage Low Level Input Voltage CLK High Level Input CLK Low Level Input High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Input Capacitance Output Capacitance Clock Capacitance Min 2.5 - 0.5 3.7 - 0.5 3.0 -- -- -- -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- Max 5.25 0.8 5.25 0.8 -- 0.45 15 15 10 15 20 Unit V V V V V V A A pF pF pF fc = 1 MHz fc = 1 MHz fc = 1 MHz Condition TTL Level TTL Level CMOS Level CMOS Level IOH = 1 mA IOL = 4 mA
MC143421 2
MOTOROLA
Table 1. Pin Descriptions
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Signal Name C/BE[3]# IDSEL GND VCC AD[23] AD[22] AD[21] AD[20] GND AD[19] AD[18] AD[17] AD[16] VCC GND C/BE[2]# FRAME# IRDY# GND TRDY# DEVSEL# STOP# PAR GND VCC C/BE[1]# AD[15] AD[14] AD[13] GND AD[12] AD[11] AD[10] AD[9] GND AD[8] C/BE[0]# AD[7] AD[6] GND VCC AD[5] I/O I/O I I/O I/O I/O I/O I/O I/O I I/O I/O I/O O O O O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O Type I I PCI Bus Command and Byte Enable PCI Initialization Device Select; Chip Select for Configuration Read and Write Cycles Ground Power 5 V PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data Ground PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data Power 5 V Ground PCI Bus Command and Byte Enable PCI Cycle Frame; Indicates the Beginning and Duration of a Bus Access PCI Initiator Ready; Indicates the Bus Master's Ability to Complete the Current Data Phase of the Transaction Ground PCI Target Ready; Indicates the Target Agent's Ability to Complete the Current Data Phase of the Transaction PCI Device Select for Configuration Read and Write Cycles PCI Stop; Indicates the Current Target Request for Transceiver Termination Indicates Even Parity Across AD[31:0] and C/BE[3:0]# Ground Power 5 V PCI Bus Command and Byte Enable PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data Ground PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data Ground PCI Bus Multiplexed Address and Data PCI Bus Command and Byte Enable PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data Ground Power 5 V PCI Bus Multiplexed Address and Data Function
MOTOROLA
MC143421 3
Table 1. Pin Descriptions (continued)
43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 AD[4] AD[3] AD[2] GND AD[1] AD[0] READ WRITE RESET GND VCC ha[3] ha[2] ha[1] ha[0] GND hd[7] hd[6] hd[5] hd[4] hd[3] hd[2] VCC GND hd[1] hd[0] aux[7] aux[6] aux[5] aux[4] GND PME# NC NC NC NC VCC aux[3] aux[2] aux[1] aux[0] GND INTA# RST# O I I/O I/O I/O I/O OC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I/O I/O O O O I/O I/O I/O PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data Ground PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PIB Read Strobe PIB Write Strobe PIB Reset -- Generated by PCI Reset Ground Power 5 V PIB Address -- Subsystem ID (Sampled at Reset) PIB Address -- Subsystem ID (Sampled at Reset) PIB Address -- Subsystem ID (Sampled at Reset) PIB Address -- Subsystem ID (Sampled at Reset) Ground PIB Data -- Subvender ID (Sampled at Reset) PIB Data -- Subvender ID (Sampled at Reset) PIB Data -- Subvender ID (Sampled at Reset) PIB Data -- Subvender ID (Sampled at Reset) PIB Data -- Subvender ID (Sampled at Reset) PIB Data -- Subvender ID (Sampled at Reset) Power 5 V Ground PIB Data -- Subvender ID (Sampled at Reset) PIB Data -- Subvender ID (Sampled at Reset) PIB Programmable General Purpose I/O (See Figure 1) PIB Programmable General Purpose I/O (See Figure 1) PIB Programmable General Purpose I/O (See Figure 1) PIB Programmable General Purpose I/O (See Figure 1) Ground PCI Power Management Event No Connect No Connect No Connect (Or 10 k Resistor Pull-Down -- See Device Class Section) No Connect (Or 10 k Resistor Pull-Down -- See Device Class Section) Power 5 V PIB Programmable General Purpose I/O (See Figure 1) PIB Programmable General Purpose I/O (See Figure 1) PIB Programmable General Purpose I/O (See Figure 1) PIB Programmable General Purpose I/O (See Figure 1) Ground PCI Interrupt PCI Device Reset
MC143421 4
MOTOROLA
Table 1. Pin Descriptions (continued)
87 88 89 90 91 92 93 94 95 96 97 98 99 100 CLK NC NC GND VCC AD[31] AD[30] AD[29] AD[28] GND AD[27] AD[26] AD[25] AD[24] I/O I/O I/O I/O I/O I/O I/O I/O I PCI Bus Clock No Connect No Connect Ground Power 5 V PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data Ground PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data PCI Bus Multiplexed Address and Data
NOTE: A # symbol at the end of a signal name indicates that it is active low and connects to the PCI Bus (per PCI specification conventions). An overbar symbol also indicates the pin is active low and connects to the Peripheral Interface Bus (per Motorola specification conventions).
REG 02h[5:0]
6
REG 03h[5:0]
6
6
AUX[5:0]
REG 02h[7:0]
2 REG 03h[6] CONFIG 44h[0] A0 B0 2 REG 03h[7] CONFIG 44h[1] A1 B1 A/B 2 AUX[7:6]
REG 2bh[0]
PME#
8
8
REG 29h[7:0] 8 8 8 AUX[7:0] REG 2ah[7:0]
INTA#
8
8
REG 05h[7:0]
Figure 1. Logical Equivalence of AUX Pin Control Register
MOTOROLA
MC143421 5
hd[7:0] ha[3:0] READ WRITE RESET AUX[0] AUX[1] AUX[2:4] AUX[5] AUX[6] AUX[7]
H[7:0] HA[3:0] HRD HWR RESET CS INT MISC CONTROL WAKEUP POWERSTATE[1] POWERSTATE[0]
MC143421
DSP
PCI BUS
Figure 2. Typical Implementation
MC143421 6
MOTOROLA
Table 2. PCI Configuration Space Description Please reference PCI Specification 2.1 and "Addition of PME# Signal to Connector" ECN.
Offset 00h 02h 04h Bits 15:0 31:16 29 28 26:25 20 2 1 0 08h 31:8 7:0 0ch 23:16 15:8 10h 31:8 7:1 0 14h 31:12 11:1 0 2ch 31:20 19:16 15:8 7:0 34h 3ch 7:0 15:11 10:8 7:0 40h 44h 31:0 15 Type RO RO RO RO RO RO RO RW RW RO RO RO RO RW RO RO RW RO RO RO RO RO RO RO RO RO RW RO RW Vendor ID Device ID Master Abort Target Abort Medium Device New Capabilities (ACPI) Master Enable Memory Enable I/O Enable PCI Multimedia Device Revision ID Header Type Latency Timer 256-Byte I/O Space I/O Size I/O Space Indicator 4K Memory Space Memory Size Memory Space Indicator Subsystem ID Subsystem ID Subvendor ID Subvendor ID Cap_Ptr (ACPI) Interrupt Pin INTA# Interrupt Line PMC (ACPI) PEN_status -- This bit is set when the function would normally assert the PME# signal independent of the state of the PME_En bit. Writing a 1 to this bit will clear it and cause the function to stop asserting a PME# (if enabled). Writing a 0 has no effect. PEN_EN -- A 1 enables the function to assert PME#. When 0, PME# assertion is disabled. PowerState -- This two-bit field is used both to determine the current power state of the function and to set the function into a new power state. The definition of the field values is given below: 00b D0 01b D1 10b D2 11b D3hot 6c210001h 0h 0b 0h From ha[3:0] During Reset 0h From hd[7:0] During Reset 40h 0h 1b 0h 1b 048000h 00h 0h 2100000h Description Value 1057h 3421h
8 1:0
RW RW
NOTES: 1. RO: Read Only Register 2. RW: Read and Write Register 3. All other registers not shown in the table will return 0s.
MOTOROLA
MC143421 7
PERIPHERAL INTERFACE BUS
Pin Description
Signal Type Output Output Output Output In/Out
Pin RESET READ WRITE ha[3:0] hd[7:0]
Description Reset Signal, Active Low Read Command Pulse Signal, Active Low Write Command Pulse Signal, Active Low 4-Bit Address Bus 8-Bit Data Bus
ripheral function. In the event of a PCI I/O read operation, and if the address is qualified for the address mapping of the PIB, the READ control signal on the PIB will be activated for at least three PCI cycles. The input data, from the eight-bit data port on the PIB, will be latched on the rising edge of the READ signal and transferred to the PCI bus. The PCI address bus is driven by the MC143421 one cycle prior to the falling edge of the READ pulse and at least one cycle after the rising edge or the READ pulse. The setup and hold time for the MC143421 to successfully latch the data from the PIB is 3 ns. PCI Write Operation The write operation is complementary to the read with the same timing, the data and address information on the PIB is valid one cycle prior to the falling edge of the PIB WRITE pulse. The data will remain valid until one cycle after the rising edge of the PIB WRITE pulse. The address valid time is the same as the read operation. Subsystem ID and Subvendor ID When the MC143421 is reset, the states of the hd[7:0] and ha[3:0] pins are read into the subsystem ID and subvendor ID registers. The inputs are matched to register 2Ch as shown in Table 3. Pins hd[0] and ha[0] are internally lightly pulled up, and hd[7:1] and ha[3:1] are internally lightly down. If these pins are left floating on reset, the resulting subsystem and subvendor IDs will be 1. External pullups and pulldowns are required for unique subvendor and subsystem IDs. Device Class The MC143421 is classified as a PCI Multimedia Device. Pins 77 and 78 are internally lightly pulled down, and can be left as no connects, or externally pulled down. If either of these pins are pulled up, it will result in an invalid vendor and device ID.
Address Mapping
A31:A8 PCI A31 to A8 equal to config register 10h A7 1 A6 1 A5 ha [3] A4 ha [2] A3 ha [1] A2 ha [0] A1 X A0 X
A31 to A8 from the PCI bus are compared to the value in configuration register 10h, when a match occurs and both A7 and A6 are equal to 1, the lower eight bits are mapped as follows: A5 mapped to ha[3] A4 mapped to ha[2] A3 mapped to ha[1] A2 mapped to ha[0] A0 and A1 are ignored PCI Read Operation The MC143421 will translate the PCI I/O cycle to the ISA- like Peripheral Interface Bus (PIB) that connects to the pe-
Table 3. Register 2Ch
31 0 30 0 29 0 28 0 27 0 26 0 25 0 24 0 23 0 22 0 21 0 20 0 19 ha3 18 ha2 17 ha1 16 ha0
Subsystem ID
15 0
14 0
13 0
12 0
11 0
10 0
9 0
8 0
7 hd7
6 hd6
5 hd5
4 hd4
3 hd3
2 hd2
1 hd1
0 hd0
Subvendor ID
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MOTOROLA
INTERNAL REGISTER DESCRIPTION
Offset 00h Bits 0 1 2 3 5:4 Description External reset, controlling pin ERESET on the PIB Reserved Reserved Reserved 00: PIB three-cycle operation 01: PIB five-cycle operation 1-: PIB twelve-cycle operation Reserved Reserved Reserved AUX pin control register. The corresponding AUX pin is an output when set to 1. AUX pin data register. When AUX pin is set as an output, the output state will be controlled by this register. Reserved Interrupt 1 mask register. Selects the AUX input that will generate the interrupt. Reserved AUX pin status register. Reads the status of the AUX pin. ACPI mask register. Set to 1 to select the AUX input to be used to enable PME# output. Enables an external event (such as a ring) to switch on the computer. AUX pin data polarity control register. Set to 1 to invert the polarity of data. AUX pin data select register. Bit 0 set to 1, AUX[6:7] becomes power state bit (reference PCI config register 44h[1:0]). Peripheral Interface Bus Addressing
Access Procedures All the internal registers are IO/MEM mapped. They can be accessed with either I/O or memory read/write command from the PCI bus. For I/O access, the host needs to send the address with bits A31 to A8 to match the data in configuration register 10h bits 31 to 8. Also, the address bits 7 and 6 need to be set to 0. For memory access, the address bits A31 to A12 need to match the value in configuration register 14h bits 31 to 12 and the address bits 11 to 6 need to all be 0. The internal registers are byte addressable.
6 7 01h 02h 7:0 7:0
03h
7:0
04h 05h 06h 07h 29h
7:0 7:0 7:0 7:0 7:0
2ah 2bh
7:0 0
C0 to FF
7:0
MOTOROLA
MC143421 9
PACKAGE DIMENSIONS
FU SUFFIX QFP (Quad Flat Package) CASE 842D-03
Y
80 S 81
AA
51 S 50
D
S
C A-B
-A- V L
-B- B
H A-B
S
D
P 0.05 (0.002) D
M
0.20 (0.008)
0.20 (0.008)
M
B B DETAIL A -A-, -B-, -D-
DETAIL A
100 31
Z
1
30
-D- A 0.20 (0.008)
M
F
S
H A-B S
D
S
0.05 (0.002) A-B 0.20 (0.008)
M
J
S
N
C A-B
D
S
D 0.13 (0.005) C E M DETAIL C
DATUM PLANE M
BASE METAL
C A-B
S
D
S
SECTION BB
ROTATED 90_ CLOCKWISE
-H- -C-
SEATING PLANE
H G
M
0.10 (0.004)
U
DATUM PLANE
T R
GAGE PLANE
-H- AB
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS A-B AND -D- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -C-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.46 (0.018). DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT.
K X DETAIL C
Q
DIM A B C D E F G H J K L M N P Q R S T U V X Y Z AA AB
MILLIMETERS MIN MAX 19.90 20.10 13.90 14.10 --- 3.30 0.22 0.38 2.55 3.05 0.22 0.33 0.65 BSC 0.10 0.36 0.11 0.23 0.73 1.03 12.35 REF 5_ 16 _ 0.11 0.17 0.325 BSC 0_ 7_ 0.25 0.35 23.65 24.15 0.13 --- 0_ --- 17.65 18.15 1.95 REF 0.58 REF 0.83 REF 18.85 REF 0.25 BSC
INCHES MIN MAX 0.783 0.791 0.547 0.555 --- 0.130 0.009 0.015 0.100 0.120 0.009 0.013 0.026 BSC 0.004 0.014 0.004 0.009 0.028 0.040 0.486 REF 5_ 16 _ 0.004 0.007 0.013 BSC 0_ 7_ 0.010 0.014 0.931 0.951 0.005 --- 0_ --- 0.695 0.715 0.077 REF 0.023 REF 0.033 REF 0.742 REF 0.010 BSC
MC143421 10
MOTOROLA
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MC143421/D MC143421 11

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